A. Field of the Invention
This invention relates to a multiprocessor system having a plurality of processors connected to a shared bus and a shared memory through respective private caches. More particularly, this invention relates to such a multiprocessor system adopting a so-called snoopy cache architecture wherein each private cache is provided with a controller which monitors signals on the shared bus and manipulates data in the private cache, for example, for maintaining data consistency among the private caches.
B. Related Art
While there are a number of types of conventional multiprocessor systems, tightly coupled multiprocessor systems are increasingly coming into practical use.
In one such type of tightly coupled multiprocessor system, a plurality of processors read from or write to a shared memory connected to a shared bus. Without private caches, each processor has to accomplish read/write access to the shared memory through the shared bus. Therefore the shared memory is very frequently occupied. Thus, in such an environment, an increase in the number of processors can not improve the performance of the system beyond a certain limitation.
An approach has been proposed wherein each processor has a private cache in which it keeps a partial copy of data stored in the shared memory. Each processor performs read/write access to the data within its private cache, and thereby the shared bus and memory are not used very frequently. The above described approach is commonly referred to as a multi-cache system. That approach, however, causes a problems in that when each processor modifies shared data in its cache without relation to other sharing processors, the sharing processors may, at any instant in time, have different data at a given address. Means for maintaining consistency of data at a given address in different caches is accordingly needed. Hereinafter, "the consistency of data" means that every processor looks at the same data at a given address.
One method for ensuring the consistency of data is the snoopy cache technique. The snoopy cache technique maintains the consistency of data among caches by having each processor's cache controller monitor the shared bus. That is, when a processor modifies shared data in its cache (i.e. data that is shared by one or more other processors), it sends information about how it modified the data and what address the modified data is at, on the shared bus. The cache controllers of the other processors see that information and update or invalidate the data in their caches to maintain the consistency.
Conventional snoopy cache techniques will typically adopt one of two conventional protocols to handle modification of shared data. According to the first conventional protocol, upon modification to shared data at a cache, copies at the other caches are invalidated. According to the second conventional protocol, upon modification to shared data at a cache the copies at the other caches are modified. For example, Dragon of the Xerox Corporation (U.S.A.), and FireFly of Digital Equipment Corporation (U.S.A.), use the update type. On the other hand, SPUR of the University of California uses the invalidate type. In addition to the above, TOP-1 (prototype name) of Tokyo Research Laboratory, IBM Japan Ltd., is designed to selectively switch between the update and invalidate types with implementation in software.
The above two types can equally maintain the consistency of data among a plurality of caches. That is, the updating and invalidating of data have the same effect with respect to the consistency. However they both have merits and demerits in accordance with their approaches.
The update type is suitable for cases where manipulating such data tightly shared by processors (or where the processors almost equally access shared data). The invalidate type is not suitable for those cases, because each time a processor modifies a shared data area, the copies in the caches of the other sharing processors are invalidated. Thus, a read/write access to that area by the other sharing processors inevitably causes a cache miss and requires the access to the shared bus. In this regard, the update type cache is advantageous since the copies in the sharing caches are updated, thereby enabling the processors to read the data area without accessing to the shared bus. Generally speaking, the update type works well when used for buffers in a parallel program of the producer and consumer model, and semaphore or the like used to synchronize processors, etc.
The invalidate type, on the other hand, is preferably applied to shared data which is exclusively used by one processor or to shared data to which is not accessed frequently by the other processors. Paging of process migration may cause data exclusively held by one processor to be considered shared while it should be kept as exclusive. This situation places unnecessary shared data in the system and degrades the performance. The invalidate type is effective in that situation.
In light of the strengths and weaknesses of each, a preference between the above types of protocols can not be decided in a straightforward manner in that the performance of the system under a given protocol depends on the characteristics of a program to be executed and the operational status of individual processors. Thus far, the use of the above-described conventional protocols has not enabled efficient operations in every data access situation.
The above mentioned Dragon, FireFly and SPUR each provides only one type of protocol, and consequently achieve only degraded performance in some situations. TOP-1 can selectively switch between the above mentioned types of protocols by means of software. This, however, still does not resolve the problem of how to switch. The resolution of that problem is a key factor in whether or not the performance is fully enhanced.